1. Field
Embodiments described herein relate generally to a Synchronous type semiconductor storage device and a DRAM.
2. Background Art
Recently, an increasing integration of a memory device tends to lead to an increase in the capacity of an array unit of, for example, a DRAM. Due to such tendency, the capacitance of wirings thereof also increases. Therefore, when a transistor is at the so-called slow corner of the PVT conditions (process parameters, voltage, and temperature), the read/write time of the array unit is deteriorated greatly. In addition, in a highly integrated memory device, a ratio of a read/write time to a cycle time tends to be larger.
On the other hand, although the line and space patterns of the column selection lines and the data lines of the DRAM are scaled, the R/C value of the internal wiring of the array unit is rarely scaled. Therefore, the read/write time is not reduced due to the R/C value of the internal wiring even at the fast corner of the transistor. Accordingly, it is not preferable to decrease the pulse width of the read/write pulse signal of the array unit at the fast corner.
Therefore, the read/write pulse signal may have a large duty ratio with respect to the cycle time defined as one cycle of a clock signal, and it is necessary to suppress the decrease in the pulse width at the fast corner (in other words, it is necessary to suppress the PVT change in the pulse width).
The clock signal as a trigger clock for the read/write pulse signal is input to various circuits. For this reason, it is preferable that the pulse width of the clock signal is controlled independently of the read/write pulse width.
Therefore, conventionally, an edge trigger type pulse generator has been used as a read/write pulse generation circuit. Accordingly, the pulse generator may be compatible with both of the cases: one case where the pulse width of the clock signal is smaller than the read/write pulse width and the other case where the pulse width of the clock signal is larger than the read/write pulse width.
The edge trigger type pulse generator performs a pulse reset operation by using the pulse output as a trigger. In the edge trigger type pulse generator, a reset path for resetting is longer than a path for generating a pulse, and the reset path is a rate-controlling factor at the time of generating the pulse comprising a large duty ratio with respect to the cycle time as described.
In addition, for the speedy reset operation, there is a trend that the size of the transistor used for the reset operation increases. As a result, the number of logic stages in the path for generating the pulse is also increased in order to make it possible for more driving capacity for the reset transistor to be obtained. However, the increase in the number of logic stages acts as a negative factor in suppressing the PVT change in the read/write pulse signal.